_________________________________________________________ maxim integrated products 1 some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim - ic.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1 - 888- 629- 4642, or visit maxim?s website at www.maxim - ic.com. abridged data sheet max24288 ieee 1588 packet timestamper and clock and 1gbps parallel- to - serial mii converter g eneral description the max24288 is a flexible , low - cost ieee 1588 clock and timest amper with an sgmii or 1000base - x serial interface and a parallel mii interface that ca n be configured for gmii, rgmii , or 10/100 mii. the device provides all required hardware support for high - accuracy time and frequency synchronization using the ieee1588 precision time protocol. in b oth the transmit and receive directions 1588 packets are identified and timestamped with high precision. system software makes use of these timestamps to determine the time offset between the system and its timing master. software can then correct any time error by steering the device?s 1588 clock subsystem appropriately. the device provides the necessary i/o to time - synchronize with a 1588 master elsewhere in the same system or to be the master to which slave components can synchronize. in addition , the m ax24288 is a full - featured, gigabit parallel -to - serial mii converter. it provides full sgmii revision 1.8 compliance and also interfaces directly to 1gbps 1000base - x sfp optical modules . a p p l i c a tions 1588- enabled equipment with 1g ethernet ports wireless base s tations and controllers switches, routers, dslams, pon equipment pseudowire circuit emulation equipment test and measurement systems industrial and factory automation equipment medical equipment ordering information part temp range pin - package MAX24288ETK+ -40 c to +85 c 68 tqfn - ep* + denotes a lead (pb) - free/rohs - compliant package. *ep = exposed pad. spi is a trademark of motorola, inc. hig hlighted features ? com plete hardware support for ieee 1588 ? ordinary , boundary , and transparent clocks ? flexible block for any 1588 architecture ? 1588 clock hardware ? steerable by software with 2 - 8 ns time resolution and 2 - 32 ns period resolution ? 1 ns input timestamp accuracy and output edge placement accuracy ? three time/frequency controls: d irect time write, time adjustment , and high - resolution frequency adjustment ? programmable clock and time - alignment i/o ? input event timestamper detects incoming time alignment (e.g. , 1 pps ) or cl ock edges ? output event generator provides output clock signal or time alignment signal ? built - in support for telecom equipment timing architecture with dual redundant timing cards ? 1588 timestamping hardware ? 1588 v1 and v2 packets, transmit and receive ? packe t classifier supports 1588 o ver ethernet, ipv4/udp, ipv6/udp , or mpls and i s programmable for more complex stacks ? supports 802.1q vlan tags and mac - in - mac ? one - step operation: on - the - fly timestamp insertion or transparent clock corrections; no need for follow - up packets ? can insert all timestamps, receive and transmit, into packets for easy software access ? optional two - step operation ? parallel - to - serial mii conversion ? bidirectional wire - speed interface conversion ? serial: 1000base - x or sgmii v1.8 (4, 6 , o r 8 pin) ? parallel: gmii, rgmii , or 10/100 mii ? translates link speed and duplex m ode negotiation between mdio and sgmii pcs ? full support for 1588 + synchronous ethernet ? mdio and spi ? interfaces ? 1.2v operation with 3.3v i/o 19 - 5931 ; rev 0; 6/11
max24288 2 abridged data sheet application examples example 1: single - port 1588 slave node sfp module ethernet over fiber 1.25g serial max24288 local osc gmii processor mac mdio 1588 recovered clock, e. g. 25 mhz 1588 recovered time, e.g. 1 pps 1588 software to frequency-syntonized or time-synchronized system components ethernet over copper sgmii 1000base-t phy -or- -or- example 2: multiport system with switch - connected 1588 slave node processor 1588 software sfp modules or 1000base-t phys ethernet over fiber 1.25g serial gbe switch ic sgmii to other phys max24288 local osc gmii mac mdio 1588 recovered clock, e.g. 25mhz 1588 recovered time, e.g. 1 pps to frequency-syntonized or time-synchronized system components example 3: multiport system, boundary or transparent clock, port card logic processor sfp module ethernet over fiber 1.25g serial max24288 gmii mac mdio system clock, e.g. 25mhz system time, e.g. 1 pps from central timing function ethernet over copper sgmii 1000base-t phy -or- -or- packet data to/from central switch function line clock, e.g. 25mhz line clocks from other ports to central timing function for synce or 1588 + synce operation 1588 software exam ple 4: multiport system, boundary or transparent clock, central timing function processor 1588 software system time, e.g. 1 pps to all port cards packet data to/from central switch function line clocks, e.g. 25mhz from port cards, for synce or 1588+synce operation mac max24288 1588 clock gmii mdio 1.25g serial local osc stratum 3+ ds31400 clock sync ic clk system clock, e.g. 25mhz other clocks, various frequencies
max24288 3 abridged data sheet block diagram receive gmii rgmii mii rxd[7:0] rxclk rx_dv rx_er col crs 1588 packet classifier and modifier d c d c pcs decoder (10b/8b) rd[9:0] 125mhz receive cdr rdp rdn transmit gmii rgmii mii txd[7:0] txclk gtxclk tx_en tx_er d c d c pcs encoder (8b/10b) td[9:0] 125mhz de- serializer rd 1.25ghz serializer transmit driver td 625mhz tdp tdn tclkp tclkn tx sop detect 1588 time engine ts3 time stamper time peg1 prog. event generator control and status jtag gpio control tx pll refclk 125mhz 125mhz, 62.5mhz, 25mhz, 2.5mhz 625mhz jtclk jtms jtdi jtdo mdio mdc rst_n gpio1 gpio2 gpio3 gpo1 gpo2 sclk sdi sdo cs_n max24288 auto- negotiate peg2 prog. event generator gpio4 gpio5 gpio6 gpio7 output clock generator 125mhz, 8 phases tlb loopback dlb loopback rate adaption buffer rate adaption buffer ts2 time stamper ts1 time stamper d c d c 1588 packet classifier and modifier alos rx sop detect rx sop tx sop tx sop rx sop rclk rclk rlb loopback jtrst_n detailed features general features ? control and status through mdio interface or spi interface ? high - speed mdio interface (12.5mhz slave only) with optional pre amble suppression ? optional spi 4 - wire serial microprocessor interface ( 25mhz, slave only ) ? operates from a 10, 12.8 , 25 , or 125mhz reference clock ? optional 125mhz output clock for mac to use as gtxclk parallel - serial mii conversion features ? bidirectional wi re - speed interface conversion ? serial interface: 1000base - x or sgmii revision 1.8 (4, 6 , or 8 pin s ) ? parallel interface: gmi i, rgmii (10, 100 , and 1000mbps) or 10/100 mi i (dte or dce) ? 8 - pin source- clocked sgmii m ode ? 4 - pin 1000base -x s er d es mode to in terface with optical m odules ? connects processors with parallel mii interfaces to 1000base - x sfp optical modules ? connects processors with parallel mii interfaces to phy or switch ics with sgmii interfaces ? interface conversion is transparent to mac layer an d higher layers ? translates link speed and duplex mode between gmii/mii mdio and sgmii pcs
max24288 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the r ight to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 4 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products. abridged data sheet 1588 clock features ? steerable by s oftware with 2 - 8 ns time r esolution and 2 - 32 ns period r esolution ? 1ns input timestamp accuracy and output edge placement a ccuracy ? in itialized and steered by software on an external processor to follow a n external 1588 master ? three time/frequency controls: direct time write, time adjustment, and high - resolution frequency adjustment ? programmable clock and time - alignment i/o to synchroniz e all boards in large systems o can frequency - lock to an input clock signal from elsewhere in the system o can timestamp an input time alignment signal to time - lock to a master elsewhere in the system (e.g. , 1 pps) o can provide an output clock signal to slave c omponents elsewhere in the system (125mhz / n , 1 n 255) o can provide an output time alignment signal to slave components elsewhere in the system (e.g. , 1 pps) ? input signal timestamper can stamp rising edges, falling edges or both ? flexible programmable event generator (peg) can output 1 pps, one pulse per period, and a wide variety of clock signals ? full support for dual redundant timing cards to match architecture used in sonet/sdh ? full support for switches and routers as transparent clocks or boundary clocks ? compatible with a wide vari ety of 1588 syst em architectures 1588 timestamper features ? identifies and ti mestamps 1588 v1 and v2 packets in both transmit and receive directions ? programmable packet classifier can identify packets transported by a variety of protocol stacks o 1588 over ethernet o 1588 over ipv4/udp o 1588 over ipv6/udp o 1588 over mpls o configurable for more complex stacks as well o recognizes 802.1q vlan tags and 802.1ah mac -in - mac o can be configured to identify cesop or satop for timing over adaptive - mode circuit emulation ? transmit and receive ti mestamping with 1ns resolution ? one - step operation minimizes network bandwidth consumption o on - the - fly timestamp insertion o on - the - fly corrections in transparent clocks o no need for follow - up packets ? can insert all timestamps (receive and transmit ) into packe ts for easy software access o three insert methods: direct overwrite, read - add- write, and read - subtract - write o eliminates reads from timestamp fifos o minimizes processor bus traffic ? optional two - step operation ? optional 8 - entry timestamp fifos synchronous ethe rnet features ? full support for 1588 over synchronous ethernet ? receive path bit clock can be output on a gpio pin to line - time the system from the ethernet port ? transmit path can be frequency - locked to a system clock signal connected to the refclk pin not e to readers: this document is an abridged version of the full data sheet. to request the full data sheet, go to www.maxim - ic.com/max24288 and click on request full data sheet .
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